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Embedded Systems Glossary: A
Thu, 2007-11-29 14:17 - webmaster
(ay to dee converter) n. A hardware device that reads an analog signal—typically a voltage—compares it to a reference signal, and converts the resulting percentage to a digital value. Short for analog-to-digital converter. Abbreviated ADC. The reference signal represents 100%. An n-bit A/D converter has a maximum value of 2n - 1 and a resolution of Vref/2n. [more]
See also D/A converter.
(like Cain's brother) abbr. A design language for creating the logic to be implemented in a simple programmable logic device. Short for Advanced Boolean Expression Language. Programs created with ABEL are compiled into the binary pattern necessary to create the PLD with a device programmer. [more]
adj. Denotes a logic device or circuit where a logic 1 is a lower voltage than a logic 0.
n. A set of wires connected to a processor and all of the peripherals with which it communicates, for the purpose of selecting a specific memory location or register within a particular peripheral. If the address bus contains n electrical lines, the processor can address up to 2n unique locations. Address decoding logic between the processor and the devices connected to the bus select the proper device, typically based on the uppermost bits.
1. n. Allowing one memory location or register to be accessible at more than one address. Aliasing is a result of address decoding and often happens with peripheral control and status registers. For example, if an I/O device has just four byte-wide registers but is mapped into a 256-byte region of memory, aliasing will occur. In this case, the same four registers can be read or written at any of 64 different locations within that region.
2. n. An effect, because of undersampling, where a time-varying signal appears to be running, at a much lower frequency than it really is. Aliasing is a common effect of using a digital oscilloscope to view fast waveforms, like clocks. If the scope's sampling rate is low, the perfect 20-MHz clock could appear to be oscillating at 10 kHz.
3. n. Different variables reference the same physical memory location. In languages that support pointers, it is common for a program to maintain multiple references to the same storage. Each of these references is an alias. Aliasing can create problems when optimizing compilers and pipelined processors because it becomes more difficult for them to identify and analyze data dependencies within the program.
adj. Describes data represented by a continuous range of values. The opposite of digital, in which all information is quantized. Analog is the way the world beyond the quantum level works. Part of the challenge of digital engineering is to convert noisy, inaccurate, and ugly real-world data to the pristine purity of 1s and 0s. The last two decades have seen a massive growth in digital signal processors, partly because they allow us to replace analog circuits with digital. Ultimately, the goal is to push the digital components all the way back to all systems' front ends--essentially connecting a radio's antenna, for example, directly into a DSP input.
n. The element of a semiconductor device that accepts electrons. In a diode, for example, current passes from the anode to the cathode. On a diode, the anode is the terminal not marked by a band.
adj. Lacking periodicity; random. The term is most often used in the embedded context when scheduling periodictasks via RMA. The issue of what to do about aperiodic tasks and interrupts inevitably arises in real-world systems. Aperiodic tasks become ready to run on the occurrence of unpredictable events.
EXAMPLE: The arrival of interrupts is often aperiodic.
See also sporadic.
n. Software that is specific to a particular embedded system. Such application-specific code is generally built on a layered architecture of reusable components, such as a real-time operating system and network protocol stack or other middleware. If there is no such architecture, then this term may not be used. The application software is unlikely to be reusable across embedded platforms, simply because each embedded system has a different application.
n. A piece of custom-designed hardware in a mass-produced chip. Abbreviated ASIC.
n. An infamous European rocket (made by Aerospatiale) that demonstrates the flawed principle of redundancy based on duplicated software. Unlike hardware subsystems, which either work or fail and can be made more reliable through duplication, software is either right or wrong in its logic. If software fails once, it will fail again given the same inputs; merely duplicating the code does not add redundancy.
In the case of Ariane 5, some code borrowed form the successful Ariane 4 design experienced an overflow during flight. Recognizing the overflow, the primary controller shut itself down and the secondary controller took over. Unfortunately the secondary controller experienced the very same overflow condition and shut down as well. The rocket self-destructed in midair, taking some very expensive cargo with it. [more]
See also Therac-25.
(like your arm) abbr. A 32-bit RISC processor widely used in low-power embedded applications. Short for Advanced RISC Machine.
HISTORY: The ARM design was started in 1983 as a project at Acorn Computer Group. After being refused access to the upcoming Intel 80286 for newer generations of their computer line, they responded by starting up a team to design and build a new CPU. When launched in 1985, the chip was the first commercial RISC processor.
DEC later licensed the design and produced the StrongARM. This work was later passed to Intel as part of a patent-related settlement, and Intel took the opportunity to replace their ailing i860 and i960 designs with the StrongARM. Today these are known by the name XScale.
n. A 16-bit variant of the 32-bit ARM instruction set. ARM processors that support the Thumb instruction set can be switched in and out of "Thumb mode" via a bit in a register. Once in the Thumb mode, the CPU fetches special 16-bit instructions from memory. The advantage of these instructions is that they can be fetched more quickly across a narrower data bus and consume less memory. Not all of the ARM's capabilities are supported in Thumb mode, however. [more]
(rhymes with harp) abbr. A mechanism for mapping a destination IP address to its corresponding MAC address so that an IP packet can be routed over a specific physical network such as Ethernet. Short for Address Resolution Protocol. RFC 826.
Each node on a network has both a logical (IP) address and a physical (MAC) address. When sending a packet to a specific node, the application software provides only the IP address. The protocol stack, via ARP, must determine the specific MAC address for that IP address before it can finalize and send the network frame that will contain the IP packet. In practice, it is inefficient to make ARP requests and receive replies before each packet is sent, so a table is kept (typically at the network driver) of all the known IP-MAC address pairs. Only if the MAC address of a particular destination IP address cannot be found in that table is the ARP protocol invoked. The results are added to the table then so they can be used later. [more]
See also RARP.
(ay sick) abbr. See application-specific integrated circuit.
n. A software development tool that translates human-readable assembly language programs into machine-readable code that the target processor can understand and execute.
USAGE: Assembler also can mean assembly language, as in, "I wrote that part of the code in assembler."
n. A human-writable form of a processor's native instruction set. In its typical form, each line of assembly code represents a single CPU instruction. The human-readable representation of each opcode is called a mnemonic.
GetHexByte: call SerialReceive ;get new byte from serial port addlw 0xBF ;add -'A' to ASCII high byte btfss STATUS,C ;check if positive addlw 0x07 ;if not, add 17 ('0' to '9') addlw 0x0A ;else add 10 ('A' to 'F') movwf HexByte ;save nibble swapf HexByte,F ;move nibble to high position call SerialReceive ;get new byte from serial port addlw 0xBF ;add -'A' to ASCII low byte btfss STATUS,C ;check if positive addlw 0x07 ;if not, add 17 ('0' to '9') addlw 0x0A ;else add 10 ('A' to 'F') iorwf HexByte,F ;add low nibble to high nibble movf HexByte,W ;put result in W reg return
n. A communications scheme that transmits data over a single wire, sending bits one at a time in sequence. The timing of each bit is known by both transmitter and receiver. Each transmitted data byte begins with a start bit that starts the receiver's timing circuitry. Critical to the success of a synchronous communications is that the data bits have well-defined widths.
EXAMPLE: The best known asynchronous communications scheme is RS-232.
See also start bit.
Contrast with synchronous communication.
1. adj. An operation that cannot be interrupted is considered atomic. Atomic operations are inherently reentrant; they complete without fear of preemption or corruption by other tasks. A single opcode that does a read-modify-write, for instance, modifies a shared variable without the risk of an intervening interrupt causing the variable to be used in a half-changed state. Software developers can turn non-natomic operations into atomic ones by disabling interrupts. See also swap, test-and set.
2. adj. Used to indicate measurements scales. Atomic scales are on the order of angstroms.
(at vef) abbr. A standard for creating enhanced, interactive television content and for delivering that content to a range of television, set-top, and PC-based receivers. Short for Advanced TV Enhancement Forum (http://www.atvef.com). ATVEF defines the standards used to create enhanced content that can be delivered over a variety of media, including analog (NTSC) and digital (ATSC) television broadcasts, and a variety of networks, including terrestrial broadcasts, cable, and satellite. It is based on HTML. [more]
n. The average amount of time to execute a section of code. It may be helpful to define the jitter and standard deviation along the average-case execution time might be interesting in some applications, the worst-case execution time is typically of far more interest, particularly in real-time systems.